cy25560 spread spectrum clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07425 rev. *f revised september 11, 2009 features 25 mhz to 100 mhz operating frequency range 9 different spread select options accepts clock and crystal inputs low power dissipation: ? 56 mw at fin = 25 mhz ? 89 mw at fin = 65 mhz ? 139 mw at fin = 100 mhz frequency spread disable function center spread modulation low cycle-to-cycle jitter 8-pin soic package commercial and industrial temperature ranges applications desktop, notebook, and tablet pcs vga controllers lcd panels and monitors printers and multifunction devices (mfp) benefits peak electromagnetic interference (emi) reduction by 8 to 16 db fast time to market cost reduction vss pd reference divider loop filter 1 2 modulation control input decoder logic feedback divider vco divider & mux 8 3 cp ssclk s0 s1 6 7 5 4 20 k 20 k 20 k 20 k sscc vdd xout xin/ clk vdd vdd vss vss 250 k logic block diagram [+] feedback
cy25560 document #: 38-07425 rev. *f page 2 of 9 pinouts figure 1. pin configuration ? 8-pin soic package general description the cypress cy25560 is a spread spectrum clock generator (sscg) ic used to reduce the emi found in today?s high-speed digital electronic systems. the cy25560 uses cypress?s pr oprietary phase-locked loop (pll) and spread spectrum clock (ssc) technology to synthesize and frequency modulate the input frequency of the reference clock. by frequency modulating the clock, the measured emi at the fundamental and harmonic frequencies of clock (ssclk) is greatly reduced. this reduction in radiated energy can significantly reduce the cost of complying with regul atory requirements and time to market without degrading system performance. the cy25560 is a very simple and versatile device to use. the frequency and spread% range is selected by programming s0 and s1 digital inputs. these inputs use three (3) logic states including high (h), low (l) and middle (m) logic levels to select one of the nine available spread% ranges. refer to ta b l e 2 for programming details. cy25560 is optimized for svga (40 mhz) and xvga (65 mhz) controller clocks and also suit able for applications where the frequency range is 25 mhz to 100 mhz. a wide range of digitally selectable spread percentages is made possible by using three-level (high, low, and middle) logic at the s0 and s1 digital control inputs. the output spread (frequency modulation) is symmetrically centered on the input frequency. spread spectrum clock control (sscc) function enables or disables the frequency spread and is provided for easy comparison of system performance during emi testing. the cy25560 is available in an 8-pin soic package with 0 c to 70 c commercial and ?40 c to 85 c industrial operating temperature ranges. table 1. pin description pin number pin name type pin description 1xin/clki clock or crystal connection input . refer to ta b l e 2 for input frequency range selection. 2vddp positive power supply . 3gndp power supply ground . 4 ssclk o modulated clock output, which is the same frequency as the input clock or the crystal frequency . 5 sscc i spread spectrum clock contro l (enable/disable) function . sscg function is enabled when input is high and disabled when input is low. this pin is pulled high internally. 6s1i tri-level logic input control pin used to select input frequency range and spread percent . refer to tri-level logic on page 3 for programming details. pin 6 has an internal resistor divider network to v dd and v ss . refer to logic block diagram on page 1. 7s0i tri-level logic input control pin used to select input frequency range and spread percent . refer to tri-level logic on page 3 for programming details. pin 7 has an internal resistor divider network to v dd and v ss . refer to logic block diagram on page 1. 8xouto oscillator output pin connected to crystal . leave this pin unconnected if an external clock is used to drive x in /clk input (pin 1). 1 2 3 4 8 7 6 5 xin/clk vdd vss xout s0 s1 sscc cy25560 ssclk [+] feedback
cy25560 document #: 38-07425 rev. *f page 3 of 9 figure 2. three-level logic examples tri-level logic with binary logic, four stat es can be programmed with two control lines, whereas three-level logic can program nine logic states using two control lines. three-level logic in the cy25560 is implemented by defining a third logic state in addition to the standard logic ?1? and ?0?. pins 6 and 7 of the cy25560 recognize a logic state by the voltage applied to their respective pin. these states are defined as ?0? (low), ?m? (middle), and ?1? (one). each of these states have a defined voltage range that is interpreted by the cy25560 as a ?0?, ?m?, or ?1? logic state. refer to ta b l e 3 for voltage ranges for each logic state. the cy25560 has two equal value resistor dividers connected internally to pins 6 and 7 that produce the default ?m? (midd le) state if these pins are left unconnected (nc). pins 6 and/or 7 can be tied directly to ground or v dd to program a logic ?0? or ?1? state, respectively. sscg theory of operation the cy25560 is a pll-type clock generator using a proprietary cypress design. by precisely controlling the bandwidth of the output clock, the cy25560 becom es a low-emi clock generator. the theory and detailed operation of the cy25560 is discussed in the following sections. emi all digital clocks gener ate unwanted energy in their harmonics. conventional digital clocks are square waves with a duty cycle that is very close to 50%. because of this 50/50 duty cycle, digital clocks generate most of their harmonic energy in the odd harmonics, i.e., third, fifth, sevent h, etc. it is possible to reduce the amount of energy contai ned in the fundamental and odd harmonics by increasing the band width of the fundamental clock frequency. conventional digital clocks have a very high q factor, which means that all of the energy at that frequency is concentrated in a very narrow bandwidth, consequently, higher energy peaks. regulatory agencies test electronic equipment by the amount of peak energy radiated from the equipment. by reducing the peak energy at the fundamental and harmonic frequencies, the equipment under test is able to satisfy agency requirements for emi. conventional methods of reducing emi have been to use shielding, filter ing, multilayer pcbs, etc. the cy25560 uses the approach of reducing the peak energy in the clock by increasing the clock bandwidth, and lowering the q factor. cy25560 cy25560 cy25560 7 6 5 vdd s0 = "m" (n/c) s1 = "0" (gnd) 7 7 6 6 5 5 vdd vdd vdd s0 s1 s0 s0 s1 s1 sscc = "1" sscc = "1" s1 = "0" (gnd) s0 = "1" s0 = "1" s1 = "1" sscc = "1" 25 ? 50 mhz (low range) input frequency (mhz) s1=m s0=m (%) s1=m s0=0 (%) s1=1 s0=0 (%) s1=0 s0=0 (%) s1=0 s0=m (%) 25 ? 35 4.3 3.8 3.4 2.9 2.8 35 ? 40 3.9 3.5 3.1 2.5 2.4 40 ? 45 3.7 3.3 2.8 2.4 2.3 45 ? 50 3.4 3.1 2.6 2.2 2.1 50 ? 100 mhz (high range) input frequency (mhz) s1=1 s0=m (%) s1=0 s0=1 (%) s1=1 s0=1 (%) s1=m s0=1 (%) 50 ? 60 2.9 2.1 1.5 1.2 60 ? 70 2.8 2.0 1.4 1.1 70 ? 80 2.6 1.8 1.3 1.1 80 ? 100 2.4 1.7 1.2 1.0 select the frequency and center spread % desired and the n set s1, s0 as indicated. select the frequency and center spread % desired and the n set s1, s0 as indicated. table 2. frequency and spread% selection [+] feedback
cy25560 document #: 38-07425 rev. *f page 4 of 9 sscg sscg uses a patented technology of modulating the clock over a very narrow bandwidth and controlled rate of change, both peak and cycle-to-cycle. the cy25560 takes a narrow band digital reference clock in the range of 25 to 100 mhz and produces a clock that sweeps between a controlled start and stop frequency and precise rate of change. to understand what happens to a clock when sscg is applied, consider a 65 mhz clock with a 50% duty cycle. from a 65 mhz clock we know the following: if this clock is applied to the xin/clk pin of cy25560, the output clock at pin 4 (ssclk) sweeps back and forth between two frequencies. these two frequencies, f1 and f2, are used to calculate to total amount of spread or bandwidth applied to the reference clock at pin 1. as the clock is making the transition from f1 to f2, the amount of time and sweep waveform play a very important role in the amount of emi reduction realized from an sscg clock. the modulation domain analyzer is used to visualize the sweep waveform and sweep period. figure 3 shows the modulation profile of a 65 mhz sscg clock. notice that the actual sweep waveform is not a simple sine or sawtooth waveform. figure 3 also shows a scan of the same sscg clock using a spectrum analyzer. in this scan you can see a 6.48 db reduction in the peak rf energy when using the sscg clock. modulation rate spectrum spread clock generators utilize frequency modulation (fm) to distribute energy over a specific band of frequencies. the maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies. the time required to transition from fmin to fmax and back to fmin is the period of the modulation rate, tmod. modulation rates of sscg clocks are generally referred to in terms of frequency or fmod = 1/tmod. the input clock frequency, fin, and the internal divider count, cdiv, determine the modulation rate. in some sscg clock generators, the selected range determines the internal divider count. in other sscg clocks, the internal divider count is fixed over the operating range of the device. the cy25560 has a fixed divider count of 1166. figure 3. sscg clock, cy25560, fin = 65 mhz tc = 15.4 ns 50 % 50 % clock frequency = fc = 65 mhz clock period = tc =1/65 mhz = 15.4 ns device divider count (cdiv) cy25560 1166 (all ranges) example: device = cy25560 fin = 65 mhz range = s1 = 1, s0 = 0 then: modulation rate = fmod = 65 mhz/1166 = 55.7 khz. modulation profile spectrum analyzer [+] feedback
cy25560 document #: 38-07425 rev. *f page 5 of 9 cy25560 application schematic the schematic in figure 4 demonstrates how the cy25560 is configured in a typica l application. this application is shown as using a 30 mhz fundamental crystal. in most applic ations, an external reference clock is used. apply the external clock signal at xin (pin 1) and leave xout (pin 8) unconnected (see ta b l e 1 for pin descriptions). contact cypress if higher order crystal is to be used. figure 4. application schematic vdd 1 8 y1 30 mhz sscc vss s1 s0 xin/clk xout ssclk vdd cy25560 5 7 6 4 0.1 uf c3 c2 c3 27 pf 27 pf 2 3 vdd [+] feedback
cy25560 document #: 38-07425 rev. *f page 6 of 9 absolute maximum ratings commercial grade [1, 2] supply voltage (v dd ):.....................................?0.5v to +6.0v dc input voltage: ................................... ?0.5v to vdd+0.5v junction temperature ................ .............. ... ?40c to +140c operating temperature:...................................... 0c to 70c storage temperature ................. .............. ... ?65c to +150c static discharge voltage (esd) ........................... 2,000v-min notes 1. operation at any absolute maximum rating is not implied. 2. single power supply: the voltage on any input or i/ o pin cannot exceed the power pin during power up. table 3. dc electri cal characteristics v dd = 3.3v10%, t= 0c to 70c and c l (pin 4) = 15 pf, unless otherwise noted parameter description conditions min typ max unit v dd power supply range 10% 2.97 3.3 3.63 v v ih input high voltage s0 and s1 only 0.85v dd v dd v dd v v im input middle voltage s0 and s1 only 0.40v dd 0.50v dd 0.60v dd v v il input low voltage s0 and s1 only 0.0 0.0 0.15v dd v v oh output high voltage i oh = 6 ma 2.4 v v ol output low voltage i oh = 6 ma 0.4 v c in1 input capacitance xin/clk (pin 1) 3 4 5 pf c in2 input capacitance xout (pin 8) 6 8 10 pf c in2 input capacitance s0, s1, sscc (pins 7, 6, 5) 3 4 5 pf i dd1 power supply current fin = 25 mhz, cl= 0 17 23 ma i dd2 power supply current fin = 65 mhz, cl= 0 27 41 ma i dd3 power supply current fin = 100 mhz, cl= 0 42 59 ma table 4. electrical timing characteristics v dd = 3.3v10%, t= 0c to 70c and c l (pin 4) = 15 pf, unless otherwise noted parameter description conditions min typ max unit i clkfr input clock frequency range v dd = 3.30v 25 100 mhz t f clock rise time (pin 4) ssclk at 0.4 ? 2.4v 1.0 1.8 2.8 ns t r clock fall time (pin 4) ssclk at 0.4 ? 2.4v 1.0 1.8 2.8 ns d tyin input clock duty cycle xin/clk (pin 1) 25 50 75 % d tyout output clock duty cycle ssclk (pin 4) 45 50 55 % j cc1 cycle-to-cycle jitter fin = 25 mhz?50 mhz, sscc = 1 150 300 ps j cc2 cycle-to-cycle jitter fin = 50 mhz?100 mhz, sscc = 1 130 200 ps [+] feedback
cy25560 document #: 38-07425 rev. *f page 7 of 9 absolute maximum conditions industrial grade [1, 2] supply voltage (v dd ):.....................................?0.5v to +6.0v dc input voltage: ................................... ?0.5v to vdd+0.5v junction temperature ................ .............. ... ?40c to +140c operating temperature:.................................. ?40c to 85c storage temperature ................. .............. ... ?65c to +150c static discharge voltage (esd) ........................... 2,000v-min table 5. dc electrical ch aracteristics (preliminary) v dd = 3.3v10%, t= ?40c to 85c and c l (pin 4) = 15 pf, unless otherwise noted parameter description conditions min typ max unit v dd power supply range 10% 2.97 3.3 3.63 v v ih input high voltage s0 and s1 only 0.85v dd v dd v dd v v im input middle voltage s0 and s1 only 0.40v dd 0.50v dd 0.60v dd v v il input low voltage s0 and s1 only 0.0 0.0 0.15v dd v v oh output high voltage i oh = 6 ma 2.2 v v ol output low voltage i oh = 6 ma 0.4 v c in1 input capacitance xin/clk (pin 1) 3 4 5 pf c in2 input capacitance xout (pin 8) 6 8 10 pf c in2 input capacitance s0, s1, sscc (pins 7, 6, 5) 3 4 5 pf i dd1 power supply current fin = 25 mhz, cl= 0 17 24 ma i dd2 power supply current fin = 65 mhz, cl= 0 27 41 ma i dd3 power supply current fin = 100 mhz, cl= 0 42 61 ma table 6. electrical timing characteristics (preliminary) v dd = 3.3v10%, t= ?40c to 85c and c l (pin 4) = 15 pf, unless otherwise noted parameter description conditions min typ max unit i clkfr input clock frequency range v dd = 3.30v 25 100 mhz t f clock rise time (pin 4) ssclk at 0.4 ? 2.4v 1.0 1.8 3.0 ns t r clock fall time (pin 4) ssclk at 0.4 ? 2.4v 1.0 1.8 3.0 ns d tyin input clock duty cycle xin/clk (pin 1) 25 50 75 % d tyout output clock duty cycle ssclk (pin 4) 45 50 55 % j cc1 cycle-to-cycle jitter fin = 25 mhz?50 mhz, sscc = 1 150 300 ps j cc2 cycle-to-cycle jitter fin = 50 mhz?100 mhz, sscc = 1 130 200 ps ordering information part number package type product flow pb-free cy25560sxc 8-pin soic commercial, 0 c to 70 c cy25560sxct 8-pin soic ? tape and reel commercial, 0 c to 70 c cy25560sxi 8-pin soic industrial, ?40 c to 85 c CY25560SXIT 8-pin soic ? tape and reel industrial, ?40 c to 85 c [+] feedback
cy25560 document #: 38-07425 rev. *f page 8 of 9 package drawing and dimensions figure 5. 8-pin (150-mil) soic s8 51-85066-*c [+] feedback
document #: 38-07425 rev. *f revised september 11, 2009 page 9 of 9 psoc designer?, programmable system-on-chip ?, and psoc express? are trademarks and psoc? is a registered trademark of cypress s emiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i2c components from cypress or one of its sublic ensed associated companies conveys a license under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defi ned by philips. as from october 1st, 2006 philips semiconduct ors has a new trade name - nxp semiconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy25560 ? cypress semiconductor corporation, 2005-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com document title: cy25560 spread spectrum clock generator document number: 38-07425 revision ecn orig. of change submission date description of change ** 115261 oxc 06/12/02 new datasheet. *a 119441 rgl 10/17/02 corrected the values in the absolute maximum ratings to match the device. *b 122704 rbi 12/30/02 added power up requirements to maximum ratings information. *c 125549 rgl 05/15/03 added industrial temperature range to the device. removed v ol2 and v oh2 spec in the dc specs table changed idd values from 11/17/25 typ and 14/22/34max to 17/27/42 typ and 23/41/59 max changed t f /t r values from 1.3/1.3 typ and 1.6/1.6 max to 1.8/1.8 typ and 2.8/2.8 max in the electrical char. table. changed j cc1/2 values from 200/250 typ and 250/300 max to 150/130 typ to 300/200 max in the electrical char. table. changed the low power dissipation from 36/56/82mw to 56/89/139mw respectively. changed the low cycle-to-cycle jitter fr om 195/175/100ps-typ to 450/225/150 ps-max *d 314293 rgl see ecn added pb-free devices. *e 2762435 cxq/hmt 09/11/09 fixed the frequency in figure of sscg section on page 3. removed pb devices from ordering information table. *f 2819309 ved 12/01/09 m i no r change - updated revision number and corrected the document number at the beginning of this table. [+] feedback
|
